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| a FEATURES Four Independent Sample-and-Holds Internal Hold Capacitors High Accuracy: 12 Bit Very Low Droop Rate: 2 mV/s typ Output Buffers Stable for C L 500 pF TTL/CMOS Compatible Logic Inputs Single or Dual Supply Applications Monolithic Low Power CMOS Design APPLICATIONS Signal Processing Systems Multichannel Data Acquisition Systems Automatic Test Equipment Medical and Analytical Instrumentation Event Analysis DAC Deglitching CMOS Quad Sample-and-Hold Amplifier SMP04* FUNCTIONAL BLOCK DIAGRAM VDD SMP04 VIN1 S/H1 VSS VIN2 S/H2 VSS VIN3 S/H3 VSS VIN4 S/H4 VSS VOUT4 VOUT3 VOUT2 VOUT1 VSS DGND GENERAL DESCRIPTION The SMP04 is a monolithic quad sample-and-hold; it has four internal precision buffer amplifiers and internal hold capacitors. It is manufactured in ADI's advanced oxide isolated CMOS technology to obtain the high accuracy, low droop rate and fast acquisition time required by data acquisition and signal processing systems. The device can acquire an 8-bit input signal to 1/2 LSB in less than four microseconds. The SMP04 can operate from single or dual power supplies with TTL/CMOS logic compatibility. Its output swing includes the negative supply. The SMP04 is ideally suited for a wide variety of sample-andhold applications, including amplifier offset or VCA gain adjustments. One or more can be used with single or multiple DACs to provide multiple setpoints within a system. The SMP04 offers significant cost and size reduction over equivalent module or discrete designs. It is available in a 16-lead hermetic or plastic DIP and surface mount SOIC packages. It is specified over the extended industrial temperature range of -40C to +85C. *Protected by U.S. Patent No. 4,739,281. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998 SMP04-SPECIFICATIONS (@ VDD = +12.0 V, VSS = DGND = 0 V, RL = No Load, TA = Operating Temperature Range specified in Absolute Maximum Ratings, unless otherwise noted.) Parameter Linearity Error Buffer Offset Voltage Hold Step Droop Rate Output Source Current 1 Output Sink Current1 Output Voltage Range LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current DYNAMIC PERFORMANCE Acquisition Time3 Acquisition Time3 Hold Mode Settling Time Slew Rate4 Capacitive Load Stability Analog Crosstalk SUPPLY CHARACTERISTICS Power Supply Rejection Ratio Supply Current Power Dissipation 2 ELECTRICAL CHARACTERISTICS Symbol VOS VHS V/t ISOURCE ISINK OVR Conditions VIN = 6 V VIN = 6 V, TA = +25C to +85C VIN = 6 V, TA = -40C VIN = 6 V, TA = +25C VIN = 6 V VIN = 6 V RL = 20 k RL = 10 k Min -10 Typ 0.01 2.5 2.5 2 Max +10 4 5 25 10.0 9.5 Units % mV mV mV mV/s mA mA V V V V A s s s s V/s pF dB dB mA mW 1.2 0.5 0.06 0.06 2.4 0.5 VINH VINL IIN tAQ tAQ tH SR CL TA = +25C, 0 V to 10 V Step to 0.1% -40C TA +85C TA = +25C, 0 V to 10 V Step to 0.01% To 1 mV RL = 20 k <30% Overshoot 0 V to 10 V Step 10.8 V VDD 13.2 V 0.8 1 4.25 5.25 3 3.5 3.75 9 1 4 500 -80 75 4 PSRR IDD PDIS 60 7 84 (@ VDD = +5.0 V, VSS = -5.0 V, DGND = 0.0 V, RL = No Load, TA = Operating Temperature Range specified in Absolute Maximum Ratings, unless otherwise noted.) Parameter Linearity Error Buffer Offset Voltage Hold Step Droop Rate Output Resistance Output Source Current 1 Output Sink Current1 Output Voltage Range LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current DYNAMIC PERFORMANCE 2 Acquisition Time3 Acquisition Time3 Hold Mode Settling Time Slew Rate5 Capacitive Load Stability SUPPLY CHARACTERISTICS Power Supply Rejection Ratio Supply Current Power Dissipation Symbol VOS VHS V/t ROUT ISOURCE ISINK OVR VINH VINL IIN tAQ tAQ tH SR CL PSRR IDD PDIS -3 V to +3 V Step to 0.1% -3 V to +3 V Step to 0.01% To 1 mV RL = 20 k <30% Overshoot 5 V VDD 6 V Conditions VIN = 0 V VIN = 0 V, TA = +25C to +85C VIN = 0 V, TA = -40C VIN = 0 V, TA = +25C VIN = 0 V VIN = 0 V RL = 20 k Min -10 Typ 0.01 2.5 2.5 2 1 1.2 0.5 -3.0 2.4 0.5 3.6 9 1 3 500 60 75 3.5 0.8 1 11 Max +10 4 5 25 Units % mV mV mV mV/s mA mA V V V A s s s V/s pF dB mA mW ELECTRICAL CHARACTERISTICS +3.0 5.5 55 NOTES 1 Outputs are capable of sinking and sourcing over 20 mA, but linearity and offset are guaranteed at specified load levels. 2 All input control signals are specified with t R = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 3 This parameter is guaranteed without test. 4 Slew rate is measured in the sample mode with a 0 V to 10 V step from 20% to 80%. 5 Slew rate is measured in the sample mode with a -3 V to +3 V step from 20% to 80%. Specifications are subject to change without notice. -2- REV. D SMP04 ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted) Package Type 16-Lead Cerdip 16-Lead Plastic DIP 16-Lead SO * JA* JC Units C/W C/W C/W VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, 17 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.7 V, 17 V VLOGIC to DGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD VOUT to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . 20 mA (Not Short-Circuit Protected) Digital Input Voltage to DGND . . . . . . . -0.3 V, VDD + 0.3 V Operating Temperature Range EQ, EP, ES . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300C 94 76 92 12 33 27 JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for cerdip and plastic DIP packages; JA is specified for device soldered to printed circuit board for SO package. CAUTION 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; function operation at or above this specification is not implied. Exposure to the above maximum rating conditions for extended periods may affect device reliability. 2. Digital inputs and outputs are protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. Keep units in conductive foam or packaging at all times until ready to use. Use proper antistatic handling procedures. 3. Remove power before inserting or removing units from their sockets. PIN CONNECTIONS 16-Lead Cerdip 16-Lead Plastic DIP 16-Lead SO VOUT2 1 VOUT1 2 VIN1 3 NC 4 16 VDD 15 VOUT3 14 VOUT4 ORDERING GUIDE Model SMP04EQ SMP04EP SMP04ES Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Description Cerdip-16 PDIP-16 SO-16 Package Options* Q-16 N-16 R-16A 13 VSS TOP VIEW VIN2 5 (Not to Scale) 12 VIN4 S/H1 6 S/H2 7 DGND 8 11 VIN3 10 S/H4 9 S/H3 SMP04 *Q = Cerdip; N = Plastic DIP; R = Small Outline. NC = NO CONNECT CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SMP04 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. D -3- SMP04 VOUT1 VOUT2 VDD VOUT3 VOUT4 VIN1 VIN2 VSS VIN4 VIN3 S/H1 S/H2 DGND S/H3 S/H4 Dice Characteristics Die Size: 0.80 x 0.120 mil = 9,600 sq. mil (2.032 x 3.048mm = 6.193 sq. mm) WAFER TEST LIMITS Parameter Buffer Offset Voltage Hold Step Droop Rate Output Source Current Output Sink Current Output Voltage Range (@ VDD = +12 V, VSS = DGND = 0 V, RL = No Load, TA = +25 C, unless otherwise noted.) Symbol VOS VHS V/t ISOURCE ISINK OVR Conditions VIN = +6 V VIN = +6 V VIN = +6 V VIN = +6 V VIN = +6 V RL = 20 k RL = 10 k SMP04G Limits 10 4 25 1.2 0.5 0.06/10.0 0.06/9.5 2.4 0.8 1 10.8 V VDD 13.2 V 60 7 84 Units mV max mV max mV/s max mA min mA min V min/max V min/max V min V max A max dB min mA max mW max LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current SUPPLY CHARACTERISTICS Power Supply Rejection Ratio Supply Current Power Dissipation VINH VINL IIN PSRR IDD PDIS NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. -4- REV. D Typical Performance Characteristics-SMP04 10000 VDD = +12V VSS = 0V VIN = +5V RL = 10k 5 VDD = +12V VSS = 0V 3 1800 1600 VDD = +12V VSS = 0V DROOP RATE - mV/s DROOP RATE - mV/s DROOP RATE - mV/s 0 1 2 3 45 6 78 INPUT VOLTAGE - Volts 9 10 1000 1400 1 0 -1 100 1200 1000 10 -3 800 600 0 1 2 34 5 67 8 INPUT VOLTAGE - Volts 9 10 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE - C -5 Figure 1. Droop Rate vs. Temperature Figure 2. Droop Rate vs. Input Voltage (TA = +25C) Figure 3. Droop Rate vs. Input Voltage (TA = +125C) 3 2 TA = +25 C VDD = +12V VSS = 0V HOLD STEP - mV 3 2 7 VDD = +12V VSS = 0V VIN = +5V TA = +25 C VSS = 0V 6 1 1 SLEW RATE - V/ s HOLD STEP - mV 0 -SR 5 0 -1 -1 +SR 4 -2 -3 0 1 2 3 4 5 6 78 INPUT VOLTAGE - Volts 9 10 -2 -3 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE - C 3 10 11 12 13 14 15 VDD - Volts 16 17 18 Figure 4. Hold Step vs. Input Voltage Figure 5. Hold Step vs. Temperature Figure 6. Slew Rate vs. VDD 2 1 VDD = +12V VSS = 0V OFFSET VOLTAGE - mV 20 15 10 5 0 -5 -10 RL = 10k -15 -20 RL = VDD = +12V VSS = 0V 4 2 VDD = +12V VSS = 0V RL = 0 RL = 20k -2 -4 -6 -8 -10 0 1 2 3 4 5 6 78 INPUT VOLTAGE - Volts 9 10 0 1 2 34 5 6 78 INPUT VOLTAGE - Volts 9 10 RL = 10k OFFSET VOLTAGE - mV 0 RL = RL = 20k RL = 20k -1 -2 RL = 10k -3 -4 0 1 2 34 5 67 8 INPUT VOLTAGE - Volts 9 10 Figure 7. Offset Voltage vs. Input Voltage (TA = +25C) Figure 8. Offset Voltage vs. Input Voltage (TA = +125C) REV. D -5- OFFSET VOLTAGE - mV Figure 9. Offset Voltage vs. Input Voltage (TA = -55C) SMP04 0 7 OFFSET VOLTAGE - mV SUPPLY CURRENT - mA 5 +125 C 4 +25 C REJECTION RATIO - dB -1 VDD = +12V VSS = 0V VIN = +5V RL = 10k VSS = 0V RL = 90 80 70 60 50 40 -PSSR 30 20 10 6 VDD = +12V VSS = 0V VIN = +6V -2 +PSSR -3 3 -55 C 2 1 -4 -5 -55 -33 -15 5 25 45 65 85 105 125 TEMPERATURE - C 4 6 8 10 12 VDD - Volts 14 16 18 0 10 100 1k 10k 100k FREQUENCY - Hz 1M Figure 10. Offset Voltage vs. Temperature Figure 11. Supply Current vs. VDD Figure 12. Sample Mode Power Supply Rejection 2 1 0 GAIN - dB 90 45 OUTPUT IMPEDANCE - 35 30 PHASE SHIFT - Degrees 25 20 15 10 5 0 10 100 1k 10k 100k FREQUENCY - Hz 1M PEAK-TO-PEAK OUTPUT - Volts 15 TA = +25 C VDD = +6V VSS = -6V 12 0 -45 PHASE -90 -135 GAIN -180 -225 10M -1 -2 -3 -4 -5 100 9 6 3 1k 10k 100k FREQUENCY - Hz 1M 0 10k 100k 1M FREQUENCY - Hz 10M Figure 13. Gain, Phase Shift vs. Frequency Figure 14. Output Impedance vs. Frequency Figure 15. Maximum Output Voltage vs. Frequency -6- REV. D SMP04 GENERAL INFORMATION OUTPUT BUFFERS (Pins 1, 2, 14 and 15) The SMP04 is a quad sample-and-hold with each track-andhold having its own input, output, control, and on-chip hold capacitor. The combination of four high performance track-andhold capacitors on a single chip greatly reduces board space and design time while increasing reliability. After the device selection, the primary considerations in using track-and-holds are the hold capacitor and layout. The SMP04 eliminates most of these problems by having the hold capacitors internal, eliminating the problems of leakage, feedthrough, guard ring layout and dielectric absorption. POWER SUPPLIES The buffer offset specification is 10 mV; this is less than 1/2 LSB of an 8-bit DAC with 10 V full scale. Change in offset over the output range is typically 3 mV. The hold step is the magnitude of the voltage step caused when switching from sample-to-hold mode. This error is sometimes referred to as the pedestal error or sample-to-hold offset, and is about 2 mV with little variation. The droop rate of a held channel is 2 V/ms typical and 25 V/ ms maximum. The buffers are designed primarily to drive loads connected to ground. The outputs can source more than 1.2 mA each, over the full voltage range and maintain specified accuracy. In split supply operation, symmetrical output swings can be obtained by restricting the output range to 2 V from either supply. On-chip SMP04 buffers eliminate potential stability problems associated with external buffers; outputs are stable with capacitive loads up to 500 pF. However, since the SMP04's buffer outputs are not short-circuit protected, care should be taken to avoid shorting any output to the supplies or ground. SIGNAL INPUT (Pins 3, 5, 11 and 12) The SMP04 is capable of operating with either single or dual supplies over a voltage range of 7 to 15 volts. Based on the supply voltages chosen, VDD and VSS establish the output voltage range, which is: VSS + 0.05 V VOUT VDD -2 V Note that several specifications, including acquisition time, offset and output voltage compliance will degrade for a total supply voltage of less than 7 V. Positive supply current is typically 4 mA with the outputs unloaded. The SMP04 has an internally regulated TTL supply so that TTL/CMOS compatibility will be maintained over the full supply range. Single Supply Operation Grounding Considerations In single supply applications, it is extremely important that the VSS (negative supply) pin be connected to a clean ground. This is because the hold capacitor is internally tied to VSS. Any noise or disturbance in the ground will directly couple to the output of the sample-and-hold, degrading the signal-to-noise performance. It is advisable that the analog and digital ground traces on the circuit board be physically separated to reduce digital switching noise from entering the analog circuitry. Power Supply Bypassing The signal inputs should be driven from a low impedance voltage source such as the output of an op amp. The op amp should have a high slew rate and fast settling time if the SMP04's fast acquisition time characteristics are to be maintained. As with all CMOS devices, all input voltages should be kept within range of the supply rails (VSS VIN VDD) to avoid the possibility of setting up a latch-up condition. The internal hold capacitance is typically 60 pF and the internal switch ON resistance is 2 k. If single supply operation is desired, op amps such as the OP183 or AD820, that have input and output voltage compliances including ground, can be used to drive the inputs. Split supplies, such as 7.5 V, can be used with the SMP04 and the above mentioned op amps. APPLICATION TIPS For optimum performance, the VDD supply pin must also be bypassed with a good quality, high frequency ceramic capacitor. The recommended value is 0.1 F. In the case where dual supplies are used, VSS (negative supply) bypassing is particularly important. Again this is because the internal hold capacitor is tied to VSS. Good bypassing prevents high frequency noise from entering the sample-and-hold amplifier. A 0.1 F ceramic bypass capacitor is generally sufficient. For high noise environments, adding a 10 F tantalum capacitor in parallel with the 0.1 F provides additional protection. Power Supply Sequencing All unused digital inputs should be connected to logic LOW and the analog inputs connected to analog ground. For connectors or driven analog inputs that may become temporarily disconnected, a resistor to VSS or analog ground should be used with a value ranging from 0.2 M to 1 M. Do not apply signals to the SMP04 with power off unless the input current's value is limited to less than 10 mA. Track-and-holds are sensitive to layout and physical connections. For the best performance, the SMP04 should not be socketed. It may be advisable to have the VDD turn on prior to having logic levels on the inputs. The SMP04 has been designed to be resistant to latch-up, but standard precautions should still be taken. REV. D -7- SMP04 FREQUENCY DOMAIN PERFORMANCE The SMP04 has been characterized in the frequency domain for those applications that require capture of dynamic signals. See Figure 16a for typical 86.1 kHz sample rate and an 8 kHz input signal. Typically, the SMP04 can sample at rates up to 85 kHz. In addition to the maximum sample rate, a minimum sample pulsewidth will also be acceptable for a given design. Our testing shows a drop in performance as the sample pulsewidth becomes less than 4 s. 10 dB/DIV RANGE 15.0 dBm 6.0 dBm Table III shows the effect of sampling pulsewidth on the SNR of the SMP04. The recommended operating pulsewidth should be a minimum of 5 s to achieve a good balance between acquisition time and SNR for the 1.4 V p-p signal shown. For larger swings the pulsewidth will need to be larger to account for the time required for the signal to slew the additional voltage. This could be used as a method of measuring acquisition time indirectly. Table I. SNR vs. VIN Input Voltage (V p-p) 1 2 3 4 5 6 START 1 000.0 Hz STOP 100 000.0 Hz SNR (dB) -61 -53 -50 -47 -45 -44 a. 10 dB/DIV RANGE 15.0 dBm 6.3 dBm Conditions: VS = 6 V, fS = 14.4 kHz, fIN = 1.8 kHz, t PW = 10 s. Table II. SNR vs. Supply Voltage Supply Voltage (V) 10 12 14 15 16 17 2nd (dB) -49 -55 -60 -62 -63 -65 3rd (dB) -62 -71 -80 <-80 <-83 <-85 START 1 000.0 Hz STOP 100 000.0 Hz b. Figure 16. Spectral Response at a Sampling Frequency of 86 kHz. Photo (a) Shows a 20 kHz Carrier Frequency and Photo (b) Shows an 8 kHz Frequency. Table III. SNR vs. Sample Pulsewidth Optimizing Dynamic Performance of the SMP04 Various operating parameters such as input voltage amplitude, sampling pulsewidth and, as mentioned before, supply bypassing and grounding all have an effect on the signal-to-noise ratio. Table I shows the SNR versus input level for the SMP04. Distortion of the SMP04 is reduced by increasing the supply voltage. This has the effect of increasing the positive slew rate. Table II shows data taken at 12.3 kHz sample rate and 2 kHz input frequency. Total harmonic distortion is dominated by the second and third harmonics. Sample Pulsewidth ( s) 1 2 3 4 5 6 7 SNR (dB) -37 -44 -50 -54 -54.9 -55 -55.3 Conditions: VS = 6 V, VIN = 1.4 V p-p, fS = 14.4 kHz, fIN = 1.8 kHz. -8- REV. D SMP04 Sample-Mode Distortion Characteristics Although designed as a sample-and-hold, the SMP04 may be used as a straight buffer amplifier by configuring it in a continuous sample mode. This is done by connecting the S/H control pin to a logic LOW. Its buffer bandwidth is primarily limited by the distortion content as the signal frequency increases. Figure 17 shows the distortion characteristics of the SMP04 versus frequency. It maintains less than 1% total harmonic distortion over a voiceband of 8 kHz. Output spot noise voltage measures 4 nV/Hz at f = 1 kHz. 10 VS = 6V VIN = 4Vp-p 1 THD + NOISE - % different sampling frequencies of 14.4 kHz, 9.6 kHz and 7.2 kHz. The signal-to-noise ratios measure 58.2 dB, 59.3 dB and 60 dB respectively. Figure 19 depicts SMP04's spectral response operating with voice frequency of 3 kHz sampling at a 15.7 kHz rate. Under this condition, the signal-to-noise measures 53 dB. 10 dB/DIV RANGE 15.0 dBm 5.9 dBm 0.1 START 1 000.0 Hz STOP 20 000.0 Hz 0.010 Figure 19. SMP04 Spectral Response with an Input Carrier Frequency of 3 kHz and the Sampling Frequency of 15.7 kHz Sampled Data Dynamic Performance 0.001 0.0005 20 100 1k FREQUENCY - Hz 10k 100k 200k Figure 17. THD+N vs. Frequency Sampled Data Dynamic Performance In continuous sampled data applications such as voice digitization or communication circuits, it is important to analyze the spectral response of a sample-and-hold. Figures 16a and 16b show the SMP04 sampling at a frequency of 86 kHz with a 1.4 V p-p pure sine wave input of 20 kHz and 8 kHz respectively. The photos include the sampling carrier frequency as well as its multiplying frequencies. In the case of the 20 kHz carrier frequency, the second harmonic measures 41 dB down from the fundamental, because the second is dominant, the signal-to-noise ratio is -40.9 dB. The 8 kHz case produces an improved S/N performance of -48 dB. In the V.32 and V.33 modem environment, where a 1.8 kHz carrier signal frequency is applied to the SMP04, Figure 18 compares the spectral responses of the SMP04 under three 10 dB/DIV RANGE 15.0 dBm 5.9 dBm 10 dB/DIV In continuous sampled data applications such as voice digitization or communication circuits, it is important to analyze the spectral response of a sample-and-hold. Figures 16a and 16b show the SMP04 sampling at a frequency of 86 kHz with a 1.4 V p-p pure sine wave input of 20 kHz and 8 kHz respectively. The photos include the sampling carrier frequency as well as its multiplying frequencies. In the case of the 20 kHz carrier frequency, the second harmonic measures 41 dB down from the fundamental, because the second is dominant, the signal-tonoise ratio is -40.9 dB. The 8 kHz case produces an improved S/N performance of -48 dB. In the V.32 and V.33 modem environment, where a 1.8 kHz carrier signal frequency is applied to the SMP04, Figure 18 compares the spectral responses of the SMP04 under three different sampling frequencies of 14.4 kHz, 9.6 kHz and 7.2 kHz. The signal-to-noise ratios measure 58.2 dB, 59.3 dB and 60 dB respectively. RANGE 15.0 dBm 5.7 dBm 10 dB/DIV RANGE 15.0 dBm 5.2 dBm CENTER 10 500.0 Hz SPAN 19 000.0 Hz START 1 000.0 Hz STOP 12 000.0 Hz START 1 000.0 Hz STOP 12 000.0 Hz a. b. c. Figure 18. SMP04 Spectral Response with a 1.8 kHz Carrier Frequency. (a) Shows the Sampling Frequency at 14.4 kHz; it Exhibits a S/N Ratio of 58.2 dB. (b) Shows a 59.3 dB S/N at a Sampling Frequency of 8.6 kHz. (c) Shows a 60 dB S/N at 7.2 kHz. REV. D -9- SMP04 APPLICATIONS MULTIPLEXED QUAD DAC (Figure 20) The SMP04 can be used to demultiplex a single DAC converter's output into four separate analog outputs. The circuit is greatly simplified by using a voltage output DAC such as the DAC8228. To minimize output voltage perturbation, 5 s should be allowed to settle to its final voltage before a sample signal is asserted. Each sample-and-hold amplifier must be refreshed every second or less in order to assure the droop does not exceed 10 mV or 1/2 LSB. +12V 1F + +12V 0.1 F REF02 +5V SMP04 VOUT1 +12V VSS WR CS VZ 1/2 DAC8228 VREF VDD VO GND 5V TO 10V VOUT2 VSS VOUT3 DIGITAL INPUTS ADDRESS INPUTS CHANNEL DECODE S/H1 S/H2 S/H3 S/H4 VSS VOUT4 VSS DGND Figure 20. Multiplexed Quad DAC -10- REV. D SMP04 +5V AMPLIFIER A +5V D1 1N914 1/2 OP221 VIN ( 3.5V) -5V RESET PD/H POSITIVE AMPLIFIER B R3 20k D3 1N914 1/2 OP221 R4 100 G SD214 PD/H NEGATIVE D Q S2 VSS D4 G SD214 R2 100 D Q S1 VSS VDD D2 VSS VOUT POSITIVE R1 20k -5V 1/2 SMP04 VOUT NEGATIVE DGND Figure 21. Positive and Negative Peak Detector with Hold Control POSITIVE AND NEGATIVE PEAK DETECTOR WITH HOLD CONTROL (Figure 21) GAIN OF 10 SAMPLE-AND-HOLD (Figure 22) In this application the top amplifier (Amplifier A) is the positive peak detector and the bottom amplifier (Amplifier B) is the negative peak detector. Operation can be analyzed as follows: Assume that the S/H switch is closed. As a positive increasing voltage is applied to VIN, D2 turns on, and D1 turns off, closing the feedback loop around Amplifier A and the SMP04, causing the output to track the input. Conversely, in the negative peak detector circuit at the bottom, D4 turns off and D3 turns on, holding the last most negative input voltage on the SMP04. This voltage is buffered to the VO(NEG) output. As VIN falls in voltage the above conditions reverse, causing the most positive peak voltage to be held at VO(POS) output. This voltage will be held until the input has a more positive voltage than the previously held peak voltage, or a reset condition is applied. An optional HOLD control can be used by applying a logic HIGH to the PD/H inputs. This HOLD mode further reduces leakage current through the reverse-biased diodes (D2 and D4) during peak hold. This application places the SMP04 in a feedback loop of an amplifier. Because the SMP04 has no sign inversion and the amplifier has very high open-loop gain, the gain of the circuit is set by the ratio of the sum of the source and feedback resistances 8.66k 1N914 +12V 1k 1/4 OP490 100k VSS 340 +12V 1/4 SMP04 VOUT 0V TO 10V VIN 0V TO 1.0V S/H Figure 22. Gain of 10 Sample-and-Hold Amplifier to the source resistance. When a logic LOW is applied to the S/H control input, the loop is closed around the OP490, yielding a gain of 10 (in the example shown) amplifier. When the S/H control goes HIGH, the loop opens and the SMP04 holds the last sampled voltage. The loop remains open and the output is unaffected by the input until a logic LOW is reapplied to the S/H control. The pair of back-to-back diodes from the output of the op amp to the output of the track-and-hold prevents the op amp from saturating when the track-and-hold is in the hold mode and the loop is open. REV. D -11- SMP04 +12V INSTRUMENTATION AMP +12V V1 V2 VIN (0V TO 8V) S/H 0 VSS RG V2 S/H (DELAYED) 0 td t1 t2 DGND VSS AMP02 VOUT = G(V1-V2) G= 50k +1 RG VDD VSS V1 1/2 SMP04 -5V OR -12V Figure 23. Time Delta Sample-and-Difference Measurement SAMPLE AND DIFFERENCE AMPLIFIER (Figure 23) This circuit uses two sample-and-holds to measure the voltage difference of a signal between two time points, t1 and t2. The sampled voltages are fed into the differential inputs of the AMP02 instrumentation amplifier. A single resistor RG sets the gain of this instrumentation amplifier. Using two channels of the SMP04 in this application has the advantage of matched sample-and-hold performance, since they are both on the same chip. SINGLE SUPPLY, SAMPLING, INSTRUMENTATION AMPLIFIER (Figure 24) This application again uses two channels of the SMP04 and an instrumentation amplifier to provide a sampled difference signal. The sample-and-hold signals in this circuit are tied together to sample at the same point in time. The other two parts of the SMP04 are used as amplifiers by grounding their control lines so they are always sampling. One section is used to drive a guard to the common-mode voltage and the other to generate a +6 V reference to serve as an offset for single supply operation. GUARD + INPUT 1/4 +12V SMP04 50k GAIN = 0.1 F 50k RG +1 S/H 50k GUARD - INPUT 1/4 RG AMP02 REFERENCE SMP04 VOUT +12V 20k +12V GUARD DRIVE 1/4 20k 0.01 F 1/4 +6V REFERENCE SMP04 SMP04 Figure 24. +12 V Single Supply Sampling Instrumentation Amplifier with Guard Drive -12- REV. D SMP04 +15V 0.1 F +5V A1 A0 VDD VREF OUT DAC C OUT 0.1 F-1 F CERAMIC VIN S/H DB9 DB2-DB9 10-BIT COUNTER DB2 MSB LSB VSS 1/4 DAC8426 VOUT AGND DGND WR 1/4 SMP04 DGND VSS VDD 1F ANALOG RETURN DIGITAL RETURN CLOCK GENERATOR DB0 DB1 +15V AGND 1/4 AD7432 1/4 AD7400 DEGLITCH LOGIC Figure 25. DAC Deglitcher D/A CONVERTER DEGLITCHER Most D/A converters output an appreciable amount of glitch energy during a transition from one code to another. The glitch amplitude can range from several millivolts to hundreds of millivolts. This may become unacceptable in many applications. By selectively delaying the DAC's output transition, the SMP04 can be used to smooth the output waveform. Figure 25 shows the schematic diagram of such a deglitcher circuit. Two simple logic gates (an OR and a NAND gate) provide the proper timing sequence for the DAC WR strobe and the S/H control signal to the SMP04. In this example a linear ramp signal is generated by feeding the most significant eight bits of the 10-bit binary counter to the DAC. The two least significant bits are used to produce the delayed WR strobe and the S/H control signals. Referring to Figure 26a, new data to the DAC input is set up at the S/H's falling edge, but the DAC output does not change until a WR strobe goes active. During this period, the SMP04 is in a sample mode whose output tracks the DAC output. When S/H goes HIGH, the current DAC output voltage is held by the SMP04. After 1.2 s settling, the WR strobe goes LOW to allow the DAC output to change. Any glitch that occurs at the DAC output is effectively blocked by the SMP04. As soon as the WR strobe goes HIGH, the digital data is latched; at the same time the S/H goes LOW, allowing the SMP04 to track to the new DAC output voltage. Figure 26b shows the deglitching operation. The top trace shows the DAC output during a transition, while the bottom trace shows the deglitched output of the SMP04. DB0 DB1 WR 5V 1s S/H a. DLY 627.4 s 50m 1s b. Figure 26. (a) Shows the Logic Timing of the Deglitcher. The Top Two Traces Are the Two Least Significant Bits, DB0 and DB1, Respectively. These Are Used to Generate the WR and S/H Signals Which Are Shown in the Bottom Two Traces. (b) Shows the Typical Glitch Amplitude of a DAC (Top Trace) and the Deglitched Output of the AMP04 (Bottom Trace). REV. D -13- SMP04 VDD VIN VDD S/H VSS DGND N-CH P-CH CH LOGIC VOUT LOAD VSS Figure 27. Simplified Schematic of One Channel VDD +15V R3 4k R4 1k D1 C1 10 F + R1 10 1 2 3 16 15 14 13 5 R2 10k R2 10k 6 7 8 C2 1F SMP04 12 11 10 9 R2 10k R2 10k Figure 28. Burn-In Circuit -14- REV. D SMP04 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Cerdip (Q-16) 0.005 (0.13) MIN 16 0.080 (2.03) MAX 9 0.310 (7.87) 0.220 (5.59) 1 8 PIN 1 0.840 (21.34) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.320 (8.13) 0.290 (7.37) 0.100 (2.54) BSC 0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76) 15 0 0.015 (0.38) 0.008 (0.20) 16-Lead Plastic DIP (N-16) 0.840 (21.34) 0.745 (18.92) 16 1 9 8 0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.325 (8.26) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.070 (1.77) SEATING 0.045 (1.15) PLANE 0.015 (0.381) 0.008 (0.204) 16-Lead SO (R-16A) 0.3937 (10.00) 0.3859 (9.80) 16 9 8 0.1574 (4.00) 0.1497 (3.80) 1 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) x 45 0.0099 (0.25) 0.0500 SEATING (1.27) PLANE BSC 0.0192 (0.49) 0.0138 (0.35) 0.0099 (0.25) 0.0075 (0.19) 8 0 0.0500 (1.27) 0.0160 (0.41) REV. D -15- PRINTED IN U.S.A. C3131-0-4/98 |
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